The present invention relates to a semiconductor chip module, a semiconductor package having the same and a package module, and more particularly, to a semiconductor chip module for high capacity packaging, a semiconductor package having the same, and a package module that can decrease the height of a semiconductor package to realize a package with high capacity.
In general, a semiconductor packaging technology means a technology for mounting a semiconductor chip on a printed circuit board (PCB) or manufacturing a semiconductor product by electrically connecting and packaging packages that include the PCB and the semiconductor chip. In the semiconductor industry, packaging technologies for semiconductor integrated circuits have been continuously developed to meet the demands toward miniaturization and mounting efficiency. Recently, various stacking techniques have been developed to meet the demands for miniaturization and the high functionality of electric and electronic products.
The term “stack” referred to in the semiconductor industry means to vertically place at least two semiconductor chips or a semiconductor package including the semiconductor chips. By using the stacking techniques, in the case of a memory device, it is possible to realize a product having memory capacity at least twice that obtainable through semiconductor integration processes, and mounting area utilization efficiency can also be increased.
However, in a semiconductor package manufactured using the conventional stack technology, connection members such as wires and bumps are needed for electrical connections and transfer of signals between semiconductor chips or packages. Due to the presence of the connection members, a problem is that the height of the semiconductor package increases.
For example, in the case where wires are formed as connection members for electrical connections between semiconductor chips or packages, a disadvantage is that since an additional area is required to perform a wire boning process on a printed circuit board, the size of a package increases. Also, another disadvantage is that since a gap is needed for the wire bonding process in the semiconductor chips or packages, the height of a semiconductor package increases.
Moreover, in the case where bumps are formed as connection members for electrical connections between semiconductor chips or packages, a disadvantage is that since the bumps need be placed between the semiconductor chips or packages, the height of a semiconductor package increases by the height of the bumps.
Accordingly, in the conventional semiconductor package, the connection members for electrical connections between the stacked semiconductor chips and packages are formed between the semiconductor chips and packages. Accordingly, the space utilization efficiency of a semiconductor package decreases, and the height of the semiconductor package increases. As a consequence, in the conventional art described above, it becomes harder to stack an increased number of semiconductor chips or packages to realize a package with high capacity.